The present invention relates to a computer device.
A conventional computer device and a control method thereof are described with reference to FIG. 11, which illustrates a configuration of a conventional computer device. A central processing unit (CPU) 100 is connected with a read-only only memory (ROM) 2 via a ROM data bus c. The ROM 2 stores in advance a series of programs essentially composed of instructions straand data. The CPU 100 outputs an address signal a and an access signal b to the ROM 2. On receipt of the access signal b, the ROM 2 outputs a program stored at an address corresponding to the address signal a to the CPU 100 via the ROM data bus c.
Processing of an instruction performed inside the CPU 100 includes an instruction fetch cycle, an instruction decode cycle, and an execution cycle for performing execution of the instruction and the like. In the instruction fetch cycle, a program to be executed is acquired from the ROM 2. In the subsequent cycles including the instruction decode cycle, the acquired program is decoded and then subjected to actual processing such as memory access and data manipulation according to the decoded contents of the program.
The operation of the ROM 2 in the instruction fetch cycle will be described with reference to FIGS. 12 and 13.
FIG. 12 illustrates an internal configuration of the ROM 2, and FIG. 13 is a signal waveform diagram. As shown in FIG. 13, the instruction fetch cycle includes a precharge period T1 and a data determination period T2. In the precharge period the potentials at bit lines c1, c2, c3, and c4 of the ROM 2 shown in FIG. 12 are turned to a high (H) level on receipt of the access signal b such as a precharge signal. In the next data determination period T2, one signal line a1, a2, or a3 corresponding to the address signal a is selected by an address decoder 201. By this selection, N-ch transistors 200 connected to the selected signal line and also grounded are turned ON. Those among the bit lines c1, c2, c3, and c4 connected to the turned-ON transistors are then discharged with the potential thereof turned to a low (L) level, while the remaining bit lines hold the H potential. A program composed of a combination of the L and H potentials at the bit lines c1, c2, c3, and c4 is read via the ROM data bus c to the CPU 100.
Thereafter, on receipt of an instruction data determination signal (not shown), the read program is stored in an instruction register (not shown) of the CPU 100. Thus, the instruction fetch cycle is terminated.
In the conventional computer device described above, access to the ROM 2 is only once in the instruction fetch cycle. This arises the following problem. In general, each memory cell of the ROM 2 is essentially constructed of one capacitor and one transistor. With this configuration, if a bit line that is not connected to a turned-ON N-ch transistor 200 is grounded due to noise or the like while it holds the precharged potential and resultantly the H data is turned to L data, there is provided no means for correcting this error. As a result, a program may be read mistakenly from the CPU 100, and the mistakenly read program may be decoded and executed by the ROM 2.